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Memory

Design and develop the shared memory and data register components of an SoC application

SoC Blockset™ enables simulation and evaluation of shared memory transactions in Simulink®. To include a memory system in your SoC model, configure a memory controller for the desired number of memory channels, and then connect the controller to memory channel blocks for arbitrating and handling memory traffic.

SoC Blockset enables the simulation and evaluation of shared memory transactions in Simulink. Visualize post-simulation performance and bandwidth metrics before deploying to SoC device by using the Logic Analyzer app.

Blocks

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Memory ChannelStream data through a memory channel
Memory ControllerArbitrate memory transactions for one or more Memory Channel blocks
AXI4 Random Access MemoryModel random access through external memory (Since R2022b)
AXI4-Stream to SoftwareStream AXI4 data from FPGA to software (Since R2022b)
Software to AXI4-StreamStream AXI4 data from software to FPGA (Since R2022b)
AXI4 Video Frame BufferModel connection between two hardware algorithms through external memory (Since R2022b)
Memory Traffic GeneratorGenerate traffic towards memory controller
Register ChannelTiming model for transfer of register values
Interrupt ChannelSend interrupt to processor from hardware (Since R2020b)
AXI4 Master SinkReceive random access memory data
AXI4 Master SourceGenerate random access memory data
Stream Data SinkReceive continuous stream data
Stream Data SourceGenerate continuous stream data
SoC Bus SelectorConvert bus to control signals
SoC Bus Creator Convert control signals to bus
Stream FIFOControl backpressure between hardware logic and upstream data interface
Stream ConnectorConnect two IPs with data streaming interfaces
IP Core Register ReadModel register writes from software to hardware (Since R2020a)
Register ReadRead data from a register region on the specified IP core
Register WriteWrite data to a register region on the specified IP core
Stream ReadStream data from shared memory to processor algorithms
Stream WriteStream data from processor algorithms to shared memory (Since R2020b)
Video Stream FIFOControl backpressure between hardware logic and upstream video interface
Video Stream ConnectorConnect two IPs with video streaming interfaces

Apps

Logic AnalyzerVisualize, measure, and analyze transitions and states over time

Tools

Memory MapperConfigure memory map for SoC application

Topics

Design

Simulation

Measurement