Video Stream FIFO

Control backpressure between hardware logic and upstream video interface

Libraries:
SoC Blockset / Hardware Logic Connectivity

Description

The Video Stream FIFO block controls the back-pressure from the hardware logic to the upstream video interface. It also controls the flow between the upstream and downstream pixel data interfaces of hardware logic. Integrate this block as a configurable first-in, first-out (FIFO) block for AXI4 video stream applications. The block enables you to configure its depth and set its almost full threshold value.

Examples

Histogram Equalization Using Video Frame Buffer

Perform histogram equalization with HDMI input and output and using external memory for video frame buffering.

Open Script

Ports

Input

expand all

pixelIn — Input pixel data
scalar

Input pixel data from the data source. Specify this value as a scalar.

ctrlIn — Control signals accompanying input pixel data
`pixelcontrol` bus

Control signals accompanying the pixel stream, specified as a pixelcontrol bus containing five signals. The signals describe the validity of the pixel and its location in the frame.

Data Types: pixelcontrol

rdyFromDown — Ready signal from downstream interface
`Boolean` scalar

Control signal that indicates if the block can send pixel data to the downstream interface. When this value is 1 (true), the downstream interface is ready, and the block can send the pixel data. When this value is 0 (false), the downstream interface is not ready, and the block cannot send the pixel data.

Data Types: Boolean

Output

expand all

pixelOut — Output pixel data
scalar

Output pixel data to the downstream interface. The data type of this output data is the same as the data type of the input data.

ctrlOut — Control signals accompanying output pixel data
`pixelcontrol` bus

Control signals accompanying output pixel stream, returned as a pixelcontrol bus containing five signals. The signals describe the validity of the pixel and its location in the frame.

Data Types: pixelcontrol

rdyToUp — Ready signal to upstream interface
`Boolean` scalar

Control signal that indicates if the block is ready to receive pixel data from the upstream interface. When this value is 1 (true), the block is ready to accept pixel data from the upstream interface. When this value is 0 (false), the block is not ready to accept pixel data from the upstream interface.

Data Types: Boolean

Parameters

expand all

Depth of FIFO — FIFO depth
`16` (default) | positive integer

Specify the depth of the FIFO. This value must be a positive scalar integer and is the maximum number of entries that can be buffered before data gets dropped.

Almost full threshold — Almost full threshold value
`8` (default) | positive integer

Specify a value that asserts a back-pressure signal from the block to the data source.

To avoid dropping data, set a value allowing the data source enough time to react to backpressure. This value must be a positive integer and smaller than the FIFO depth.

Extended Capabilities

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool. See Use SoC Builder to Generate SoC Design.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2019a

Video Stream FIFO

Description

Examples

Histogram Equalization Using Video Frame Buffer

Ports

Input

pixelIn — Input pixel data scalar

ctrlIn — Control signals accompanying input pixel data pixelcontrol bus

rdyFromDown — Ready signal from downstream interface Boolean scalar

Output

pixelOut — Output pixel data scalar

ctrlOut — Control signals accompanying output pixel data pixelcontrol bus

rdyToUp — Ready signal to upstream interface Boolean scalar

Parameters

Depth of FIFO — FIFO depth 16 (default) | positive integer

Almost full threshold — Almost full threshold value 8 (default) | positive integer

Extended Capabilities

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

pixelIn — Input pixel data
scalar

ctrlIn — Control signals accompanying input pixel data
`pixelcontrol` bus

rdyFromDown — Ready signal from downstream interface
`Boolean` scalar

pixelOut — Output pixel data
scalar

ctrlOut — Control signals accompanying output pixel data
`pixelcontrol` bus

rdyToUp — Ready signal to upstream interface
`Boolean` scalar

Depth of FIFO — FIFO depth
`16` (default) | positive integer

Almost full threshold — Almost full threshold value
`8` (default) | positive integer

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.