Verification and Debug

R2026b
Verify and debug hardware designs by connecting an FPGA or SoC board to MATLAB or Simulink

These features provide connections between your FPGA or SoC board and your simulations in MATLAB® or Simulink®.

  • FPGA-in-the-loop (FIL) enables you to run a MATLAB or Simulink simulation that is synchronized with an HDL design running on an AMD® FPGA or SoC board.

  • FPGA data capture is a way to observe signals from your design while the design is running on the FPGA. It captures a window of signal data from the FPGA, based on your configuration and trigger settings, and returns the data to MATLAB or Simulink.

  • AXI manager provides access to live on-board memory locations from MATLAB or Simulink. You must include the AXI manager IP in your FPGA design.

To use these features, you must download the SoC Blockset™ Support Package for AMD FPGA and SoC Devices and set up your FPGA or SoC board. For more information, see Install Support for AMD FPGA and SoC Devices and Set Up AMD FPGA and SoC Devices.

These features are not available in MATLAB Online™ .

When you generate HDL code, you can optionally generate a test bench that verifies your generated HDL code against your Simulink model. You can verify the generated code by using HDL test bench. For more information on choosing the type of test bench to generate, see Choose a Test Bench for Generated HDL Code (HDL Coder).

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