Logic
用于集成电路的逻辑门，例如 CMOS AND、CMOS OR 和 CMOS NOT
结合实现布尔函数的逻辑门，产生单一逻辑输出。
Simscape 模块
| CMOS AND | Behavioral model of CMOS AND gate |
| CMOS Buffer | Behavioral model of CMOS Buffer gate |
| CMOS NAND | Behavioral model of CMOS NAND gate |
| CMOS NOR | Behavioral model of CMOS NOR gate |
| CMOS NOT | Behavioral model of CMOS NOT gate |
| CMOS OR | Behavioral model of CMOS OR gate |
| CMOS XOR | Behavioral model of CMOS XOR gate |
| D Flip-Flop | Behavioral model of D flip-flop (自 R2024a 起) |
| D Latch | Behavioral model of D latch (自 R2024a 起) |
| S-R Latch | Behavioral model of S-R Latch |
| Schmitt Trigger | Behavioral model of Schmitt trigger |
主题
- Parameterizing Blocks from Data Sheets
Overview of techniques used to specify block parameters to match the data from manufacturer data sheets.
- Selecting the Output Model for Logic Blocks
Explore the two output models available for logic blocks.
