Main Content

Program Standalone Altera FPGA Development Board from Simulink

This example shows how to target an Altera® FPGA development board for synthesis using the FPGA Turnkey workflow. For more information, see Workflows in HDL Workflow Advisor.

Before You Begin

To run this example, you must set up your synthesis tool. To learn how to set up your synthesis tool, see Synthesis Tool Path Setup.

This example uses the Altera DE2-115 development and education board. You can also try this example with a different board and specify the target interface according the interface definition of that board. To see a list of Altera boards that you can use with the FPGA Turnkey workflow, see Supported EDA Tools and Hardware.

To download the programming file, you must first connect the target device. However, if the target device is not connected, you can still generate the programming file.

FPGA Servomotor Controller with UART interface for Intel Board

Open Script

This example uses hdlcoderUARTServoControllerExampleAltera model that is designed to work with a Altera DE2-115 development and education board.

Open Model

Open the hdlcoderUARTServoControllerExampleAltera model.

open_system('hdlcoderUARTServoControllerExampleAltera')

The UART_Servo_on_FPGA subsystem receives commands through UART ports. The subsystem generates a pulse-width modulation (PWM) waveform to control a servomotor.

Select Target Device

  1. Right-click the UART_Servo_on_FPGA subsystem and select HDL Code > HDL Workflow Advisor.

  2. In the HDL Workflow Advisor, select the Set Target > Set Target Device and Synthesis Tool task.

  3. For Target workflow, select FPGA Turnkey.

  4. For Target platform, select Altera DE2-115 development and education board.

    If the board does not automatically appear in the list, select Get more boards to download the Altera FPGA Boards support package.

    The HDL Workflow Advisor automatically sets the synthesis tool based on your board selection.

  5. Click Run This Task.

Set Target Interface and Frequency

  1. In the left pane of the HDL Workflow Advisor, select the Set Target Interface task.

  2. For each port, set Target Platform Interfaces options as shown in this figure. Click Apply.

    The HDL Workflow Advisor allocates each port to a specified bit position [b] or range of bit positions [lsb:msb]. The width of the specification in bits must equal the width of the port on the DUT. When you select options, the HDL Workflow Advisor automatically allocates a bit range. You can double-click an entry in the Bit Range / Address / FPGA Pin column to edit its value.

    For detailed information about each Target Platform Interfaces option, refer to your board documentation.

    Note

    You must allocate at least one output port to the target device. If you do not allocate any ports, the Set Target Interface task displays an error and terminates.

  3. Click Run This Task.

  4. In the Set Target Frequency task, set FPGA system clock frequency to 100 MHz, then click Run This Task.

    In this example, the target frequency must be 100 MHz due to the fixed UART baud rate.

Generate Code, Synthesize, and Program Target Device

After you select the target device and configure its port interface, the HDL Workflow Advisor performs the next tasks automatically. The HDL Workflow Advisor performs these steps.

  1. Prepare the model for HDL code generation by checking the model for HDL code generation compatibility.

  2. Set HDL options in Model Configuration Parameters dialog box and generate HDL code.

  3. Execute FPGA synthesis and timing analysis using Altera Quartus® II. The HDL Workflow advisor also annotates the model with critical path information that it obtains during synthesis.

  4. Generate the programming file and use it program the device.

To program your target device, follow these steps:

  1. Open the Download to Target task group.

  2. Right-click Program Target device and select Run to Selected Task.

    The task sequence concludes by programming your target board with the generated programming file. You can then read the code generation and synthesis log files.

Related Topics