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建模

为硬件连接准备模型,添加模块以支持硬件协议

适用于 Xilinx® Zynq® 平台的模块和仿真功能。

模块

AXI4-Interface ReadRead data from IP core on Xilinx Zynq Platform
AXI4-Interface WriteWrite data to IP core on Xilinx Zynq Platform
Linux TaskSpawn task function as separate Linux thread
UDP ReceiveReceive UDP packet
UDP SendSend UDP message
VxWorks TaskSpawn task function as separate VxWorks thread
AXI4-Stream IIO WriteWrite AXI4-Stream Data using IIO
AXI4-Stream IIO ReadRead AXI4-Stream Data using IIO

函数

zynqlibOpen the Simulink Library Browser to the Embedded Coder Support Package for Xilinx Zynq Platform block library