建模
为硬件连接准备模型,添加模块以支持硬件协议
适用于 Xilinx® Zynq® 平台的模块和仿真功能。
模块
AXI4-Interface Read | Read data from IP core on Xilinx Zynq Platform |
AXI4-Interface Write | Write data to IP core on Xilinx Zynq Platform |
Linux Task | Spawn task function as separate Linux thread |
UDP Receive | Receive UDP packet |
UDP Send | Send UDP message |
VxWorks Task | Spawn task function as separate VxWorks thread |
AXI4-Stream IIO Write | Write AXI4-Stream Data using IIO |
AXI4-Stream IIO Read | Read AXI4-Stream Data using IIO |
模型设置
函数
zynqlib | Open the Simulink Library Browser to the Embedded Coder Support Package for Xilinx Zynq Platform block library |