Lookup Table

Map input pixel to output pixel using custom rule

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Libraries:
Vision HDL Toolbox / Conversions

Description

The Lookup Table block provides a custom one-to-one map between an input pixel value and an output pixel value.

Examples

Compute Negative Image

Create the negative of an image by looking up the opposite pixel values in a table.

Open Model

Ports

This block uses a streaming pixel interface with a bus for frame control signals. This interface enables the block to operate independently of image size and format. The pixel ports on this block support single pixel streaming or multipixel streaming. Single pixel streaming accepts and returns a single pixel value each clock cycle. Multipixel streaming accepts and returns a vector of M pixels per clock cycle to support high-frame-rate or high-resolution formats. The M value corresponds to the Number of pixels parameter of the Frame To Pixels block. Along with the pixel, the block accepts and returns a pixelcontrol bus that contains five control signals. The control signals indicate the validity of each pixel and their location in the frame. For multipixel streaming, one set of control signals applies to all pixels in the vector. To convert a frame (pixel matrix) into a serial pixel stream and control signals, use the Frame To Pixels block. For a full description of the interface, see Streaming Pixel Interface.

Input

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pixel — Input pixel stream
scalar | vector

For single pixel streaming, specify pixel as a scalar intensity value or a row vector of Number of components values. For multipixel streaming, specify pixel as a column vector of Number of pixels pixel intensity values. Number of pixels can be two, four, or eight. This block does not support multipixel-multicomponent streaming.

Integer and fixed-point data types larger than 16 bits are not supported. Signed data types are not supported.

Data Types: uint8 | uint16 | fixdt(0,N,F), N <= 16 | Boolean

ctrl — Control signals associated with pixel stream
`pixelcontrol` bus

The pixelcontrol bus contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

For multipixel streaming, each vector of pixel values has one set of control signals. Because the vector has only one valid signal, the pixels in the vector must be either all valid or all invalid. The hStart and vStart signals apply to the pixel with the lowest index in the vector. The hEnd and vEnd signals apply to the pixel with the highest index in the vector.

Data Types: bus

Output

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pixel — Output pixel stream
scalar | vector

The dimensions of the output pixel match the dimensions of the input pixel. The block returns the output pixel as a scalar, a row vector of Number of components values, or a column vector of Number of pixels values.

The data type is specified by the Table data parameter.

The software supports double and single data types for simulation, but not for HDL code generation.

ctrl — Control signals associated with pixel stream
`pixelcontrol` bus

The pixelcontrol bus contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

Data Types: bus

Parameters

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Table data — Map between input pixel and output pixel
`uint8(0:1:255)` (default) | vector

Map between input pixel and output pixel, specified as a row or column vector of any data type. The data type of the table data determines the data type of the output pixel. This mapping determines the one-to-one correspondence between an input pixel value and an output pixel value.

The length of the vector must be 2^WordLength, where WordLength is the size, in bits, of the input pixel. The Lookup Table block does not perform interpolation. Every input value must have a corresponding output value in the table.
The smallest representable value of the input data type maps to the first element of the table, the second smallest value maps to the second element, and so on. For example, if the input pixel has a data type of fixdt(0,3,1), the input value 0 maps to the first element of the table, 0.5 maps to the second element, 1 maps to the third element, and so on.

When the input pixel is a vector, the block replicates the lookup table for each element of the vector. In that case, the tables use VectorSize×2^WordLength memory locations.

Example: uint8(linspace(255,0,256))

Algorithms

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Latency

The latency of the Lookup Table block is 2 cycles.

Performance

This table shows the resource use after synthesis of the block for the Xilinx^® Zynq^®-7000 SoC ZC706 Evaluation Kit with single-pixel uint8 input and the default parameter settings. The design achieves a clock frequency of 649 MHz.

Resource	Usage
Slice LUTs	12
Slice Registers	47
DSP48	0
Block RAM	0

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
LUTRegisterResetType	The reset type of the lookup table output register. Select `none` to synthesize the lookup table to a ROM when your target is an FPGA. See also LUTRegisterResetType (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced in R2015a

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R2023a: Two pixels-per-clock streaming

The block now supports multipixel streams that have 2 pixels per clock cycle.

R2020b: Multipixel streaming

The Lookup Table block now supports multipixel streams. The HDL implementation replicates the algorithm for each pixel in parallel. You cannot use multicomponent and multipixel together.

For multipixel streaming, the blocks support input and output column vectors of 4 or 8 pixels. The ctrl port remains scalar, and the control signals in the pixelcontrol bus apply to all pixels in the vector.

Lookup Table

Description

Examples

Compute Negative Image

Ports

Input

pixel — Input pixel stream
scalar | vector

ctrl — Control signals associated with pixel stream
`pixelcontrol` bus

Output

pixel — Output pixel stream
scalar | vector

ctrl — Control signals associated with pixel stream
`pixelcontrol` bus

Parameters

Table data — Map between input pixel and output pixel
`uint8(0:1:255)` (default) | vector

Algorithms

Latency

Performance

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

R2023a: Two pixels-per-clock streaming

R2020b: Multipixel streaming

See Also

Blocks

Objects

Lookup Table

Description

Examples

Compute Negative Image

Ports

Input

pixel — Input pixel stream scalar | vector

ctrl — Control signals associated with pixel stream pixelcontrol bus

Output

pixel — Output pixel stream scalar | vector

ctrl — Control signals associated with pixel stream pixelcontrol bus

Parameters

Table data — Map between input pixel and output pixel uint8(0:1:255) (default) | vector

Algorithms

Latency

Performance

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

R2023a: Two pixels-per-clock streaming

R2020b: Multipixel streaming

See Also

Blocks

Objects

pixel — Input pixel stream
scalar | vector

ctrl — Control signals associated with pixel stream
`pixelcontrol` bus

pixel — Output pixel stream
scalar | vector

ctrl — Control signals associated with pixel stream
`pixelcontrol` bus

Table data — Map between input pixel and output pixel
`uint8(0:1:255)` (default) | vector

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.