Error in HDL code generation?

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Ravi
Ravi 2013-12-26
编辑： Tim McBrayer 2013-12-30
I have a digital PLL model In that i have na state flow model with simple code. when i click configuration parameters-> HDL Code Generation and select verilog option. Then if click Generate Code then the error is "a stateflow chart may have at most one input event for HDL code generation". So how to solve this error.

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回答（1 个）

Tim McBrayer
Tim McBrayer 2013-12-30
编辑：Tim McBrayer 2013-12-30
HDL Coder's Stateflow support can only support a single input event to a given chart. If a chart has multiple input events, you will need to implement the semantic for multiple events outside the chart. For some designs you may be able to simply logical-or the external input event signals together. Other designs will require more redesign.

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