Reducing resource utilisation in HDL coder generated code
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Hi,
I am generating HDL code using HDL coder in Matlab for my project.But the generated code uses more DSP48 slices than that is available in FPGA. Kindly suggest me a method to optimise code generation.I am having four FIR filter designed using Window method.I think that this condition is due to this.But I couldn't find any option in Workflow advisor nor FDA tool for optimising multipliers .Kindly suggest me a method to accomodate my code in FPGA by some method of optimisation.
Krishnakumar
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Tim McBrayer
2014-1-3
An additional possibility for multiplier optimization, if you are multiplying by constants, is to investigate the CSD and/or FCSD optimizations, if you are multiplying by constants in your filters. See the doc on Constant Multiplier Optimization for HDL Coder in MATLAB via
% web(fullfile(docroot,%20'hdlcoder/ug/constant-multiplier-optimization.html'))
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