Need help to do image processing for an image captured by Terasic 5M pixel camera connectd to Altera Cyclone II FPGA.

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Vasavi Ch
Vasavi Ch 2011-7-11
My code to capture and display image is in Verilog. I have to do image enhancement and edge detection.How can i do this in Matlab and convert it into Verilog file so that i can import it in Quartus.

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Tim McBrayer
Tim McBrayer 2011-7-11
Once you have designed and tested your algorithm in Simulink, you can use Simulink HDL Coder to convert your Simulink model into either Verilog or VHDL. You will even be able to incorporate your existing Verilog code into your Simulink simulation using EDA Simulator Link.
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Vasavi Ch
Vasavi Ch 2011-7-12
Thanks Tim. I have gone through the Simulink HDL coder.Do you have any idea on how to create a Simulink model using Embedded matlab function. My input image is RGB data and i need to give the input as RGB data and then convert it into grayscale to apply my algorithm. After that i convert this file into Verilog then i need to display the output image from my algorithm on LCD using FPGA.
Tim McBrayer
Tim McBrayer 2011-7-12
The MATLAB Function Block is supported for HDL code generation. The coding style can seem a bit unusual if you require your MATLAB code to contain state, so I recommend examining the representative code in the "Hardware Design Patterns Using the MATLAB Function Block" demo, which ships with Simulink HDL Coder.

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Harsha Vardhan Rao Avunoori
Hello Vasavi,
There is an inbuilt block in Simulink which actually allows the user to convert between various formats.As far as I remember it has a RGB to Intensity option which you can use inorder to convert it into grayscale or else you can use an embedded matlab function to convert between RGB and Gray formats.
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Vasavi Ch
Vasavi Ch 2011-7-12
I have tried the ColourSpace Conversion block but the problem with that block is I have to give the input in Double value for RGB. My inputs are coming from a wire in Verilog with 12 bits of data. So when I use the conversion block to convert the RGB data and generate verlog code its creating data types of Real and verilog wont accept real data type.

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