Block comptibility check failed

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Roger
Roger 2014-2-21
评论： Roger 2014-2-21
Hello, I'm now using HDL coder to generate VHDL code from my model named simple_timer_model. And then program it to the target device(Xilinx Zedboard). I encontered some errors and warnings in the stage 2.3 check Block Comatibility of HDL workflow adviser. Here is the list of the Warnings:
DL Code Generation Check Report for simple_timer_model/CPU Timer 0 Generated on 2014-02-21 10:37:05 The following table describes blocks for which errors, warnings or messages were reported.
Simulink Block Level Description simple_timer_model/CPU Timer 0/Triggered Subsystem1/Trigger Error'Output port 'Out1' must have an initial value of 0 for HDL code generation.
simple_timer_model/CPU Timer 0/Triggered Subsystem2/Trigger Error'Output port 'Out1' must have an initial value of 0 for HDL code generation.
simple_timer_model/CPU Timer 0/Triggered Subsystem4/Trigger Error'Output port 'Out1' must have an initial value of 0 for HDL code generation.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read TRB(5:5) WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read TRB(5:5)'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read1 WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read1'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Write1 WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Write1'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Period Register Read WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Period Register Read'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Prescale Register Read WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Prescale Register Read'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Prescale Register Read1 WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Prescale Register Read1'.
simple_timer_model/CPU Timer 0/Data Store Read WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Data Store Read'.
simple_timer_model/CPU Timer 0/Data Store Write WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Data Store Write'.
simple_timer_model/CPU Timer 0/Data Store Write1 WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Data Store Write1'.
simple_timer_model/CPU Timer 0/TIMER0PRD WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/TIMER0PRD'.
simple_timer_model/CPU Timer 0/TIMER0TCR WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/TIMER0TCR'.
simple_timer_model/CPU Timer 0/TIMER0TIM WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/TIMER0TIM'.
simple_timer_model/CPU Timer 0/TIMER0TPR WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/TIMER0TPR'.
simple_timer_model/CPU Timer 0/Triggered Subsystem/IC1 WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Triggered Subsystem/IC1'.
simple_timer_model/CPU Timer 0/Triggered Subsystem1/IC WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Triggered Subsystem1/IC'.
simple_timer_model/CPU Timer 0/Triggered Subsystem2/IC WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Triggered Subsystem2/IC'.
I use the block memory the simulate the behavior of 4 registers in the Timer module, and in the Triggerd subsystem block( with which I use to triger the signal transaction with a unity delay by pulse signal), I have configured the parameter 'InitialOutput' of block 'Out1' to [0], and the error still exist.
Please help me to debug my system design.

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采纳的回答

Tim McBrayer
Tim McBrayer 2014-2-21
编辑：Tim McBrayer 2014-2-21
For the triggered subsystem initial values: set the initial port value to 0, not [0]. You don't mention what version of MATLAB you are using, but this was an issue at one point in time. Current releases support the syntax you are using.
For the Data Store Memory issues: the Data Store Memory is not supported by HDL Coder. You can generate a library of all blocks supported by your installation of HDL Coder with the hdllib command. The complete list of supported blocks is in the documentation.
A hardware-friendly implementation for memory is available through the RAM blocks that ship with HDL Coder. There are three RAM variations included with the product. They are:
  • Single Port RAM
  • Simple Dual Port RAM
  • Dual Port RAM
Each implementation has a different interface. They can be found in the library created with hdllib, in the "HDL Demo Library" category. You can also open the HDL Demo Library directly with the command hdldemolib.
With only four storage locations, you can also consider using a Unit Delay for each of your four registers.
  2 个评论
Roger
Roger 2014-2-21
Thanks, I will try to use this lib to replace the incompatible blocks in my design.
Roger
Roger 2014-2-21
I tried to use the Simple Dual Port RAM block which I configured the Adress port width as 16. How can I initiate all contents inside this RAM and write frequently in my design in certain address of this RAM?

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