Code generation option in HDL coder for high clock frequency

2014 3 3
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更新时间：2014 3 3
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Hi,
I am working with simulink model whose code is generated by HDL coder. My design has a number of filter stages. The code generated for some filter stages performed as desired in FPGA .But when the design moves to higher clock frequencies HDL coder generated code fails to perform satisfactorily.The output waveform shows unneccessary and momentary variations contradictory to simulation output in the form of spikes.The transmitted waveform is observed by capturing the output in computer monitor using Chip Scope.Please inform me if there is any option to be activated in HDL coder for optimized clock generation in higher frequencies.
Krishnakumar

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回答（1 个）

0 个投票

  • How did you arrive at the clock frequency? Did you set it as a synthesis constraint? Was that constraint met? What was the clock frequency ISE reported and what have you set the frequency to when running on the FPGA? Do you see the same glitches when you slow down the clock?
  • Are you registering your outputs? If not, it’s possible you may see glitches especially if there is a combinational path from a register to the point where you inserted the chipscope.

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