I have a simple simulink DSP model using HDL Coder library. The design captures a input signal and gives it to two Discrete FIR Filters with Fully Serial Architectures. Then the output of FIR filters are converged and sent to output as a complex number.
Both FIR Filters have 100 taps (100 coefficients) but after generating the HDL Code using HDL Advisor tool, I looked inside the generated VHDL code and saw that the latency of one filter is 96 cycles and the latency of the other filter is 100 cycles. Meaning the first filter has 4 zero coefficients.
Also after looking inside the generated timing controller, I saw that the clock enable of output (ce_out) signal is generated using a counter counting 2400 cycles, meaning the output becomes valid in 1 clock cycle in each 2400 clock cycles. I am assuming this is because the hdl generator has calculated the least common multiple (lcm) of the FIR filter latencies (lcm(100,96) = 2400)). This is very undesired to me because I wanted the latency to be 100 cycles.
I have a few questions:
- What can I do to reduce the latency to 100 cycles in this model? (I don't think simply adding 4 delays to the first FIR output would solve the problem because the latency will still be 96 cycles.)
- Is there any way to tell the FIR filter to ignore optimizing zero coefficients and have a 100 cycle latency?
I believe the FIR filter needs more configuration parameters to be added.
I thought delay balancing is supposed to handle this kinda synchronizations but apparently not.
I also considered using the discrete fir filter HDL Optimized block but the block's behavior when using Fixed-point tool for fixed point conversion was inconsistent and undesired, also integrating a block depending on valid and ready control signals in a system where other blocks don't support such data propagation control signals did not seem a reasonable choice. Please tell me if any further data or details are needed.
Matlab Release: R2020b
Thanks,
Ali
