Matlab SoC BlockSet RFSoC Example cannot use different number of samples per clock cycle

2 次查看（过去 30 天）

Yaddehi De Silva 2021-9-7

0
链接

此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/1448694-matlab-soc-blockset-rfsoc-example-cannot-use-different-number-of-samples-per-clock-cycle

评论： Yaddehi De Silva 2021-9-16

I am trying to create a simple RF SoC loopback design started from simulink example. I changed the RF Data converter parameters as shown in the attached figure. When I applied this changes the stream data width get changed to 64 bit which is correct. However, when I close this dialog and repoen it the stream data width is shown as 32 as shown in the figure. It seems the data bus remains 32 bit regardless what value is selected for samples per clock cycle. If I try to run simulate with the shown configuration I get an error about data type mistmatch between uint64 and uint32. Could you please let me know what is causing this issue ? or suggest an workaround.

Thank you for your support.

I have explained in details the steps I have followed in my blog

Also I'm running Matlab 2021a on Ubuntu and my SoC Blockset version is 21.1.1

1 个评论
显示 -1更早的评论隐藏 -1更早的评论

Yaddehi De Silva 2021-9-16

This issue is a mistake from my end. The stream data width and stream clock frequency values do get changed after applying and reopening. However, the correct values are used in the simulation and model compilation. The error I received was due to not changing AdcData but from uint32 to uint64 in model browser.