How to Configure "use ieee.std_logic_unsigned.all; " in HDL Coder

Question

Ashish Kumar 2015-3-15

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https://ww2.mathworks.cn/matlabcentral/answers/183272-how-to-configure-use-ieee-std_logic_unsigned-all-in-hdl-coder

回答： Tim McBrayer 2015-3-16

采纳的回答： Tim McBrayer

Is it possible to configure HDL Coder to generate VHDL code using "use ieee.std_logic_unsigned.all; " package ?

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Answer 1

Tim McBrayer 2015-3-16

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https://ww2.mathworks.cn/matlabcentral/answers/183272-how-to-configure-use-ieee-std_logic_unsigned-all-in-hdl-coder#answer_171496

The use of std_logic_unsigned, while convenient, is not supported by HDL Coder. Many people in the industry feel the use of the std_logic_unsigned and std_logic_signed packages can lead to a lack of clarity in VHDL code. The explicit use of the signed, unsigned, and std_logic types is a code style that leads to an unambiguous definition of each signal's type and an indication of what operations are permitted. This style is what is supported by HDL Coder.