tristate input in hdl verifier?

4 次查看（过去 30 天）

Poorren 2022-11-14

Hi guys,

I met a problem on how to generate tristate bus stimulus in hdl verifier. In details, I need to verify a bus read/write.

So, the data bus need to driven as high impedance during read cycle.

Based on my knowledge, it seems that there's not way to do so. I wonder there is another possible way to accomplish this.

Thanks advance!

Regards,

Jeff

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

在 Help Center 和 File Exchange 中查找有关 Xilinx Zynq Platform 的更多信息

Find the treasures in MATLAB Central and discover how the community can help you!

Translated by