DTC-SVPWM for 4-phase SRM

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Mohammed Amin
Mohammed Amin 2023-5-14
评论： Meznane Aymen Oussama 2024-3-12
Hello,
I need help with my simulink simulation for DTC-SVPWM of 4-phase switched reluctance motor in order to finish my project of Master's degree. I am struggling and having difficulties in desingning the necessary blocks for of the SVPWM.
Can you help me to get the space vector pulse width modulation for the case of 4-phases, please ?
Thank you all
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Meznane Aymen Oussama
Meznane Aymen Oussama 2024-3-12
hello amin can you give me simulation for DTC-SVPWM of 4-phase switched reluctance motor in order to finish my project you will help me a lot

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Shaik
Shaik 2023-5-14
Hi Amin,
Certainly, I can provide some guidance on implementing space vector pulse width modulation (SVPWM) for a 4-phase switched reluctance motor in Simulink.
The first step is to define the reference signals for the SVPWM. For a 4-phase motor, you will need to generate four reference signals, one for each phase. The reference signals will represent the desired DC voltage level for each phase, which will be used to generate the pulse width modulated output signals.
Next, you will need to generate the switching signals for the inverter. You can generate the switching signals using the SVPWM algorithm, which involves calculating the duty cycles for each phase based on the reference signals and the position of the space vector.
In Simulink, you can use the "Space Vector PWM" block to implement the SVPWM algorithm. This block takes in the reference signals for each phase, as well as the electrical angle of the rotor, and outputs the PWM signals for each phase. You can connect the outputs of the "Space Vector PWM" block to the gate driver output blocks that control the inverter switches.
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Mohammed Amin
Mohammed Amin 2023-5-14
Hi Shaik,
Thank you for answering my question. Well, for more understanding, I am using PI controllers for both flux and torque (after estimating the flux and torque through alpha-beta voltages and currents generated from the converter ) where their outputs are going to be connected to the SVM block. Here i find a problem with the connections and the SVPMW block.

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