If you are referring to the latency of the system due to registers in the path between input and output, a valid flag is typically modeled as an output of the design to indicate that data is ready.
This valid flag in the Simulink simulation should go high when the data is ready on the output. Once you verify this working in your Simulink design, you can generate HDL code for it and you will find the same valid output available in HDL as well.
