Too much varying signal output due to memory block

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Jung Sunghun
Jung Sunghun 2024-1-13
评论： Paul 2024-1-16
Hello all,
This is Sunghun and I am currently trying to solve the too-varying signal output originating from using a memory block as shown below.
[Without memory block]
[With memory block]
As shown in the above two comparison captures, in contrast to the nicely smoothed graph shown in the first capture, the second capture shows a signal that quickly varies up and down. This output signal results in unwanted motor control PILS as shown in the video (https://youtube.com/shorts/zNUw8Bz_LZg).
I have played around to remove this too much varying signal output due to the memory block by changing the internal selection option provided in the memory block without any success. Is there anyone familiar with this kind of issue?
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Jung Sunghun
Jung Sunghun 2024-1-14
编辑：Jung Sunghun 2024-1-14
Thank you very much for your valuable time to review my question. Here are the answers to your questions.
Q1. In the "without memory block" model, does the signal d_1_hat show up in the SMC block through a companion "From" block?
>> No, the companion "From" block of the d_1_hat "To" block shows up in the upper level as shown below. In the following capture, the "controller_smc" is the one without a memory block and the one below representing "PIL" is the one with a memory block.
Q2. The "with memory block" model includes a lot of other blocks at the bottom of the diagram besides the addition of the Memory block. What happens if you remove the Memory block from that model and keep all of those new blocks?
>> If I remove the memory block and leave the additional blocks, it results "algebraic loop error" as shown below. This is the reason why I added the memory block.
Q2 (Extra) Even if I remove the additional components in the "with memory block" model and leave the memory block, the same simulation result is obtained as shown below. This is the reason why I am guessing the memory block results in this unwanted behavior (i.e., a signal that quickly varies up and down).
Q3. What happens if you add only the Memory block to the "without memory block" model?
>> If a memory block is added to the "without memory block" model, the resultant signal shows more peaks at two points as shown below.
In conclusion, this unwanted behavior, i.e., too-varying signal output, is coming from the memory block having a characteristic of delaying one integration step. Should I rather focus on solving algebraic loop errors again instead which I do not prefer since I already tried so many times without success?
Paul
Paul 2024-1-16
Is te only difference between the models under Q2 and Q3 the use of the d_1_hat From/Goto? Could the non-existence of d_1_hat in Q2 be impacting the results?

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