Hi Hadia,
I understand that you are experiencing an issue where PWM signal is expected to generate at frequency of 20kHz but outputting at a lower frequency.
The below listed could be the possible reasons for PWM frequency drop
- When you have multiple blocks (like ADCs, PR controllers, and PWM) operating at the same sample rate, the overall execution time of your model may exceed the allowed period for the PWM output.
- This can cause the system to effectively lower the PWM frequency to accommodate the longer execution time.
- You mentioned that replacing the sine block with a buffer resolved the issue, it suggests that the sine block may have introduced additional computational delays, affecting the model’s timing.
To resolve this issue, you can follow the below steps:
- Ensure that all components in your model are set to the same sample time (0.05 ms for 20 kHz). If any block has a different sample time, it can lead to timing mismatches, resulting in unexpected behavior.
- Use the Fixed-Step solver in your model configuration to ensure consistent sample times across blocks.
- Use the “Simulink Profiler” to analyze the execution time of different blocks and identify any that may be causing delays. You can refer to the below documentation link for more information on Simulink Profiler. https://www.mathworks.com/help/releases/R2023a/simulink/slref/simulinkprofiler.html
You can also refer to this example that demonstrates using ADC blocks to sample analog voltage and control PWM duty cycles.
Hope this answers your query!
