Ethernet-Based AXI Manager Error

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Andrea 2024-5-21

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此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/2121246-ethernet-based-axi-manager-error

评论： Abhishek Kumar Singh 2024-5-22

Hello,

I am trying to implement MathWorks example described in: https://www.mathworks.com/help/hdlverifier/xilinxfpgaboards/ug/access-fpga-mem-using-ethernet-aximaster.html

The board I am trying to use is the Xilinx AC701. Reading throughout MathWorks documentation there is nothing that indicates the example could not work for this board. It is just not part of the supported boards but the specifications are very similar to the one being used in that example (KC705).

I was able to implement the example in my board’s FPGA and I can see the ethernet port alive in my PC using WireShark. However, I am not able to create an aximanager ethernet object as the following error appears:

Error using hdlverifier.AXIManagerUDP

Unable to ping the device. Please check the hardware IP address, the Ethernet cable connection, and the configuration of the

Network Interface Card.

Error in hdlverifier.AXIManagerUDP

Error in aximanager

I set the PC IP to 192.168.0.10 and the gateway to 192.168.0.2

This is what I se on the ethernet status:

The code I am using to create the aximanager object is:

  hDDR = aximanager('Xilinx','interface','Ethernet', ...
                   'DeviceAddress','192.168.0.2');
  writememory(hDDR,'00000000',100);
  readmemory(hDDR,'00000000',1);