Hi @ Thomas J Kelly,
To address your query regarding, “However, when I run the addAXI4StreamInterface() function, a prequisite to writing to the port from MATLAB for testing purposes, I am getting data mismatch errors that can be resolved by changing the inteface width to 64 bits. So, clearly the programmed FPGA is expecting the function to request 64 bits and not 128.”
Please see my response to your comments below.
After reviewing the documentation of your evaluation kit board ZCU216,
https://docs.amd.com/r/en-US/ug1390-zcu216-eval-bd/PS-DDR4-SODIMM-Socket
I found out that it features features a 64-bit DDR4 SODIMM memory, which implies that many components in the system, including those related to memory interfaces and possibly certain IP cores, are optimized for 64-bit data paths. Also, PL DDR4 I/F consists of two banks of 32-bit components which might influence how data is handled in your design. Furthermore, if the IP core or peripheral you are interfacing with is built to operate at a maximum of 64 bits (i.e., two 32-bit channels), attempting to push 128 bits may lead to mismatches in expected data sizes which aligns clearly with your statement “ programmed FPGA is expecting the function to request 64 bits”.
Now addressing your query about, “My question is: what kind of troubleshooting steps are aviailable for an issue like this? Trying to explore these functions, you run into .p files quickly, so it's been impossible so far to see what's going on under the hood.”
Engage with Xilinx community forums or technical support for insights from others who might have encountered similar issues.
