To use the digital IO (e.g. PMOD0_0) pins on the ZCU111 and ZCU216 boards without a pre-existing block in the library in Simulink, you can follow the below steps:
- Develop Custom IP by using HDL Coder or write your custom Verilog/VHDL code to interface with the PMOD pins.
- Import your custom IP as an HDL block into Simulink using the SoC Blockset.
- Ensure that your custom HDL code properly maps the physical I/O pins and configure the FPGA pin constraints file (XDC file) to map the I/O signals to the corresponding PMOD pins on the ZCU board.
- Design a Simulink model that represents the logic you want to deploy to the digital I/O.
- Use HDL Coder to generate HDL code for the design.
- Synthesize and implement the generated HDL code in Xilinx Vivado, ensure that PMOD pins are set as the I/O in the constraints file.
You can refer the below links for more info on:
- · Integration of Custom HDL Code: https://www.mathworks.com/help/soc/ug/import-custom-hdl-ip-into-soc-blockset-design.html
- · SoC Builder: https://www.mathworks.com/help/soc/ref/socbuilder.html
