Unable to tune buck multiloop controller by using Closed-Loop PID Autotuner

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Djordje
Djordje 2024-11-26
编辑： Antonino Riccobono 2024-11-27
Dear power-electronics community,
I've tried to use Closed-Loop PID Autotuner component for the multiloop control system, based on the following examples:
1) https://www.mathworks.com/help/slcontrol/ug/bldc-motor-speed-control-with-cascade-pi-controllers.html
2) https://www.mathworks.com/help/slcontrol/ug/tune-pid-controller-in-real-time-using-closed-loop-pid-autotuner-block.html
Controller is about to control buck converter modeled in simscape.
I've tried to run the autotuning for the inner (current) loop first, and afterwards, for the outer (voltage) loop, with taking estimated gains in the current loop controller.
After trying with different combinations of start/stop periods, 'Target bandwidth', 'Target phase margin', I still have very bad response.
Seems that I am really missing something.
Could you please support?
The whole environment can be found in the attachments (ticket_autotuning.zip), and it is being started by running "init_and_start.m" script.
BR,
Djordje

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回答（1 个）

Antonino Riccobono
Antonino Riccobono 2024-11-27
编辑：Antonino Riccobono 2024-11-27
Dear Djordje,
Please, have a look at the systematic workflow explained in the following technical article I coauthored: https://www.mathworks.com/company/technical-articles/cascade-digital-pid-control-design-for-power-electronic-converters.html
Notice that I did not use the Closed-Loop PID Autotuner, but other tools that provide equivalent functionalities.
Good luck,
Antonino
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Djordje
Djordje 2024-11-27
Hi Antonio,
Thanks for the clarification.
I've finished current loop tuning (step 6), but seems that it always generates very agressive parameters, espetially "I" part, and duty behaves in the way that it takes MIN or MAX value of the saturation. I've tried to play around a little bit with bandwidth and phase margin, but didn't manage it to have less agressive control.
What is your opinion about it? Could it be that I wrongly executed a step in the guideline?
I am attaching some pictures and .zip file of the current progress in the project. System gets prepared when executing freq_resp_est_init.m.
Antonino Riccobono
Antonino Riccobono 2024-11-27
编辑：Antonino Riccobono 2024-11-27
Hi Djordje,
The fact that you are not getting your desired closed-loop performance may come from multiple sources that are hard to identify. At this stage of the design, I would give a try reducing the bandwidth. Try with 10e4 rad/s first. If you get the same oscillatory behaviour, you may want to try a sluggisher bandwidth, for example equal to 10e3 rad/s - be careful with this choice as you may need to increase the phase margin to something like 70 or 80 deg. If even this tuning results in oscillatory response, it may be either something incorrect in the model (sample times) or you missed out something in previous steps.
I do not know if you are aware that MathWorks Training Services offers the Power Electronics Control Design training course I authored where you can hands-on learn and master the systematic control design workflow it is described in the technical article. In the appendix of the course you can also find the text and solution of the exercise of the cascade control for the buck converter of the technical article.
Hope this helps,
Antonino

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