- Clock Frequency: 125MHz
- Clock Pin number: H16
How can I establish hardware-in loop implementation of PYNQ-Z2 on MATLAB using filWizard?
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Hello, I am trying to connect my Xilinx FPGA board (PYNQ-Z2) from TUL with MATLAB and perform hardware in loop simulation on Simulink. However, I am not able to establish connection between FPGA and MATLAB. Could you please guide me what steps do I need to follow to solve this error.
To stop the test, press "Ctrl+C" in the MATLAB console window.
Starting FPGA-in-the-Loop test ...
Generating FPGA programming file ...Passed
Programming FPGA ...Passed
Running FIL simulation ...Failed
Error:Failed to initialize the RTIOStream library.


(a) Xilinx PYNQ-Z2 FPGA board (b) Shorted JTAG Enable Pins
The configuration that I have done on the "New FPGA Board Wizard" for adding customized boards in MATLAB HDL Coder are as shown below.




For you kind reference, I am using
OS: Ubuntu 22.04.5 LTS OS,
FPGA: Xilinx PYNQ-Z2 (from TUL),
MATLAB Version: R2024b
Vivado Version: 2023.2 (ML Standard)
Any suggestions and support would be greatly appreciated. Thank you in advance for your time and support.
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回答(1 个)
YP
2024-12-28
Please try the following changes in the FPGA board wizard:
Also connect the Ethernet port of this board to another Gig Etherner port, e.g. from PC/Switch/Router, using a Ethernet cable, since the Ethernet PHY should be active to generate the PL clock.
Run the validation step again.
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YP
2025-2-28
The FIL test passed for me. I am using the same jumper setting as you did, and Ethernet is not connected. I've attached my zipped board file. It should be the same as yours anyway.
By the way, I am testing on Windows. There could be driver issues on your Ubuntu. Try manually installing the FTDI driver and Adept runtime.
And can you try on a Windows machine?

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