Code Generation for Delay block generates continuous if statement for loading initial value

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Hello, I have the following model:
it is a delay block with that should use the input at the first time step as the value.
In the generated code I see that in the initialize function it is setting "untitled_DW.icLoad = true" such that it loads the value on the first execution. However this generates an if statement that only needs to be checked at the 1st iteration, is it possible to have this load statement in the initialize function such that it is removed from the step the function?
/* Model step function */
void untitled_step(void)
{
/* Delay: '<Root>/Delay' incorporates:
* Inport: '<Root>/Input'
*/
if (untitled_DW.icLoad) {
untitled_DW.Delay_DSTATE = untitled_U.Input;
}
/* Outport: '<Root>/Out' incorporates:
* Delay: '<Root>/Delay'
*/
untitled_Y.Out = untitled_DW.Delay_DSTATE;
/* Update for Delay: '<Root>/Delay' incorporates:
* Inport: '<Root>/Input'
*/
untitled_DW.icLoad = false;
untitled_DW.Delay_DSTATE = untitled_U.Input;
}
/* Model initialize function */
void untitled_initialize(void)
{
/* InitializeConditions for Delay: '<Root>/Delay' */
untitled_DW.icLoad = true;
}
  3 个评论
Jake Gareau
Jake Gareau 2025-1-6
This code block is not stand alone and is being integrated into a base Software, so In this case the initialization function is called at a time when I know the initial value.
in this case is it possible to change the generation behaviour ?

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回答(1 个)

Githin George
Githin George 2025-1-15
Hi Jake,
I think this behaviour in code generation is expected for “Initial Condition through input port” after looking at the generated code pattern for “Initial Condition” block as well. Both these settings generate code with the “icLoad” flag to control initialization.
Also, from what I could see it is not really recommended for C/C++ production code, atleast for the “Initial Condition” block. Please refer to the documentation here:
Additionally, the “icLoad” flag usage may be related to other features such as “Enabled Subsystem” or “Triggered Subsystem” where the initial condition is set based on the input signal at a later timestep.

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