Hi Klemen,
The software loopback you mention here is a "remnant" coming from the source model. Before running the HDL Workflow Advisor, you have to define in/outports in the FPGA subsystem in order to be able to map these signals to physical interfaces in step 1.3 of the HDL Workflow Advisor. Since these ports inevitably generate signals in the layer above this sybsystem, a software loopback is modelled in this example to simulate the behavior expected in real-life (when the signals will be carried over the cable from the DAC to the ADC in a real loopback) and to validate the FPGA logic design directly in Simulink.
After the FPGA logic is translated into a configuration file (bitstream) by the HDL Workflow Advisor, these ports are not cleaned up automatically in the generated model. If you deploy this model on the hardware, these signals will most likely stay at zero (you can explore what they are mapped to in the generated model by going under the mask of the FPGA subsystem). You can cleanup all blocks and connections from terminated input ports and from grounded output ports using the function "speedgoat.hdlc.cleanGeneratedModel", more information about it here:
I hope this is helpful!
Dimitri
