How to send data from an RFSoC device to the Host PC?
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Dear all,
I am using AMD Zynq Ultrascale+ ZCU111 evaluation board for a simple receiver design.
Currently I record a signal from an ADC and stream it to the processing system using AXI4-Stream to Software. I can generate a bitstream using SoC Builder, run the external mode model and see the recorded signal.
The question is now how to write, e.g., 1ms of this data stream to a file on the host PC? (e.g. for the FPGA algorithm verification)
Thank you!
UPD: I received an answer from a MATLAB support, will update this question as soon as I try whether this works or not.
回答(1 个)
Abhishek
2025-9-1,8:23
编辑:Abhishek
2025-9-1,13:44
Hi @Sergei
You can capture the "AXI4-Stream" data to a file on your host PC using Simulink's "External" Mode. Here's the direct method:
Step 1: Add and Configure the “Sink” Block:
- In the Simulink model that contains the software task add a `To File` block. This can be found in the Simulink library under Simulink > Sinks. You need to connect the output of the `AXI4-Stream` to Software block to the input of this `To File` block.
- Now, Double-click the `To File` block and set the `FileName` to the file name(for eg: `adc_data.mat`) and set the `SaveFormat` parameter to `Array`.
- Provide a name for the variable that will be saved inside the MAT-file. The corresponding block parameter is `MatrixName`.
Step 2: Enable Data Archiving:
- Open the model’s configuration by going to Modeling > Model Settings > Code Generation > External Mode.
- Check the box for `Enable data archiving`. This is important for saving the file to the host PC
Step 3: Set Duration:
- Set the model's `Stop time` to the desired capture length, for this case, it is 1ms at 100 MSPS, so set it as 100000 samples).
Step 4: Build, Run, and Capture:
- Use the `SoC Builder` tool to generate the bitstream and software applications. From the Hardware tab in the Simulink toolstrip, click “Monitor & Tune”.
- Simulink will now connect to the ZCU111 and run the model. The 'adc_data.mat' file containing the captured stream will appear in the MATLAB working directory.
You can refer to the following official documentations of MATLAB:
- `To File`: https://mathworks.com/help/releases/R2025a/simulink/slref/tofile.html
- External Mode: https://mathworks.com/help/releases/R2025a/soc/ug/generate-soc-design.html#mw_a9082c63-d515-44aa-90ac-7dc799663c36
I hope this helps.
3 个评论
Abhishek
2025-9-1,13:42
Hi @Sergei
- So basically this is a two way process, first, in your main design model (before building), you connect your FPGA signal to the "AXI4-Stream IIO Write" block. This creates the hardware path to send data to the processor. Then, after you run the SoC Builder, you open the generated external mode model. In that model, a "From IIO Device" block will have appeared. That block is your signal, now available to the software. You connect that block to your Scopes or a "To File" block.
- My bad, I will fix the link.
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