Issues with Device Tree Compilation and FPGA Data Capture on ZedBoard

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덕용 2025-8-29，11:06

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https://ww2.mathworks.cn/matlabcentral/answers/2179677-issues-with-device-tree-compilation-and-fpga-data-capture-on-zedboard

评论： 덕용 2025-9-5，2:48

Hello,

I am trying to implement my algorithm on an FPGA using a ZedBoard. I have successfully completed an FPGA-in-the-Loop (FIL) test. However, my target sampling period is very short, and due to the limitations of Ethernet communication, I cannot exchange data at the microsecond level during FIL.

To address this, I am attempting to use the data capture feature by generating an IP core. I am using the HDL Workflow Advisor, and when I set the target reference design, I received the following warning:

Warning: Devicetree include directory "dts_repository\kernel_dtsi" specified by plugin "ZedBoard.plugin_board" could not be found. This may cause issues for device tree compilation and affect target device programming.

I ignored this warning and proceeded with the HDL Workflow Advisor. The HDL workflow progressed smoothly, and the FPGA bitstream was successfully built.

However, in the final step, Program Target Device, I encountered the following error:

Task "Program Target Device" unsuccessful. See log for details.

Generated logfile: hdl_prj\hdlsrc\SOGI_test2\workflow_task_ProgramTargetDevice.log

Device tree compilation failed with message:

Error executing command "dtc -@ -I dts -O dtb -o /tmp/tmp.SLNqEG/devicetree_SOGI_test2.dtb /tmp/tmp.SLNqEG/devicetree_SOGI_test2.dts". Details:

STDERR: FATAL ERROR: Couldn't open "zynq-zed.dtsi": No such file or directory

I am unsure how to resolve this issue and would greatly appreciate guidance.

Additional questions:

I am trying to capture data at the microsecond level. Is this the correct workflow for doing so? I have limited experience with FPGA development.
Why is it that on the ZedBoard, the FPGA data capture storage type seems to be limited to internal memory only?

Thank you in advance for your help

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Answer 1

Shantanu 2025-9-4，17:40

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https://ww2.mathworks.cn/matlabcentral/answers/2179677-issues-with-device-tree-compilation-and-fpga-data-capture-on-zedboard#answer_1570072

Hello 덕용,

The error FATAL ERROR: Couldn't open "zynq-zed.dtsi" means that the build process cannot find the base "map" file that describes the ZedBoard's hardware to the processor. This file is provided by a specific MATLAB add-on. Please follow these steps.

1. Open the Add-On Manager in MATLAB (Home->Add Ons->Manage Add-Ons)

2. Search for HDL Coder Support Package for AMD FPGA and SoC Devices.

3. If this package is not installed, install them else try reinstalling.

4. Ensure the installation finishes completely without any network errors or interruptions.

5. After the package is installed, delete your old project folder (hdl_prj) to ensure you start fresh.

6. Run the HDL Workflow Advisor again from the beginning. The initial warning should now be gone

These documentations might come handy

https://www.mathworks.com/help/releases/R2025a/hdlcoder/hdl-ip-core-generation.html

https://www.mathworks.com/help/hdlcoder/gs/language-and-tool-version-support.html

https://www.mathworks.com/help/hdlcoder/supported-hardware.html

As for the additional questions, workflow seems correct based on information shared, following documentations will further clarify the same.

https://www.mathworks.com/help/hdlverifier/fpga-data-capture.html