Hi All,
I have found the solution. Xilinx University Program (XUP) provides a Hardware Cosim via point-to-point Ethernet plugin for the Atlys board. It also includes the JTAG plugin (but this can be created by oneself using the "New Hardware Compilation Target" option via the System Generator block -> Hardware Cosimulation option.
To download the plugin go to XUP website -> click on "Teaching Materials" pulldown menu on RHS of website -> Download "DSP Design Flow" files -> Look in "Labsource" folder.
Read the System Generator User Guide for information on how to setup and perform HW-CoSim via Ethernet.
Regards,
William Knox