I am doing something similar, with a 512-point FFT. To keep things simple for a classroom exercise, I am starting with 384 data points, inserting 128 pilots and zeroes, using the streaming FFT with Re-Im swaps at input and output to make it an IFFT, and then inserting a 128-long cyclic prefix. Thus, I need to support three data rates with a 384:512:640 = 3:4:5 ratio and a least common multiple of 3*4*5 = 60. From a common fast sample rate, I count down by 20 to enable the data input block, by 15 for to enable the FFT, and by 12 to enable the channel drive.
The problem is that the HDL Coder demo streaming FFT block cannot be used inside an enabled subsystem for HDL Code generation, although it does work fine in simulation, so I think the only solution is to use three independent clock domains with rate transition blocks at the parallel structures, where the pilots and the cyclic prefixes are added in parallel at the frame rate, which is common for all three domains.
Simulink HDL Coder does not handle multiple clock domains and multirate transitions easily and elegantly -- as you pointed out, this is why Verilog and VHDL exist in the first place. I often use HDL Coder to save me some time by generating one or more large blocks, such as the FFT, and then I resort to hand-stitching these together into my handcrafted multiclock top level entity/module.
