Hallo
So i have my model, where 44.1 kHz signal comes in and the output is 11.28 MHz. I am using FIR interpolation filter for up sampling the input signal. I use HDL coder to generate the VHDL code and download the design to a FPGA, i am using 22.56 MHz as my FPGA system clock. But at the output i get some corrupted results and it looks like my output has a Fs of 22.56 MHz.
I am using pipelines in my filter design to increase the timing constraints. And when i compare the generated model results with my simulation results, i can see some error. For example at some points when my simulink simulation result is 1, the generated model result goes to 0 and vice versa. Any idea why this is happening?
What could be the solution, or any test to identify the problem
