How to write condition written in matlab with vhdl ?

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afef
afef 2017-7-10
i wrote a condition with matlab and i wanted to converted to vhdl i tried but i still got error message. Can anone help me please ? the code matlab:
if energie >= 96.35
fprintf('normal\n' );
elseif amplitudemin >= -185.7 & ecarttype <= 59.35 & energie<= 19.95
fprintf('normal\n' );
elseif amplitudemax >= 200.4 & ecarttype <= 59.35 & energie <= 19.95
fprintf('normal\n' );
else
fprintf('abnormal\n' );
end
the code vhdl that i tried
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY essai IS
PORT (amplitudemin,amplitudemax,ecarttype,Ea,Ed2 : IN real;
y : OUT string);
END essai;
ARCHITECTURE behavior OF essai IS
BEGIN
PROCESS (amplitudemin,amplitudemax,ecarttype,Ea,Ed2) -- liste de sensibilité
BEGIN
if( Ea >= '96.35')
y <= 'normal';
elsif (amplitudemin >= '-185.7') AND (ecarttype <= '59.35') AND (Ed2 <= '19.95')
y <= 'normal';
elsif (amplitudemax >= '200.4') AND (ecarttype <= '59.35') AND (Ed2 <= '19.95')
y <= 'normal';
ELSE
y <= 'abnormal';
END IF;
END PROCESS;
END behavior;

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