FPGA in loop for Spartan 6 SP601 board.

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Prashant Funde 2017-8-4

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此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/351508-fpga-in-loop-for-spartan-6-sp601-board

I want to use FPGA in loop with my Spartan 6 SP601 Evaluation board. I tried FIL_PID.mdl example with MATLAB2012a and ISE 14.4 . Bit file is generated and downloaded the same into board as per necessary setting.

http://in.mathworks.com/help/hdlverifier/examples/verify-hdl-implementation-of-pid-controller-using-fpga-in-the-loop.html

I followed all the steps given in this example. I wanted to know that, When i need to customise a board then i am using MATLAB 2015 because in MATLAB2012a this functionality is not given. So MATLAB2015 and ISE14.4 are compatible or not?

Please suggest me an example which I can check on Spartan6 SP601 board using FPGA in Loop.