Thanks for your question.
Simulink Design Verifier does not support models with InitFcn callbacks because in some rare cases these callbacks can change model contents and parameters within the model after the model has been translated for analysis. This would result in Design Verifier analyzing model behavior that is different than your simulation behavior.
Please consider moving the content of your InitFcn callback to the model PostLoadFcn callback:
fcn = get_param(model,'InitFcn');
set_param(model, 'PostLoadFcn', fcn);
set_param(model, 'InitFcn', '');
More information about model callbacks is available here: https://www.mathworks.com/help/simulink/ug/model-callbacks.html
