Change standard in HDL workflow adviser

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Hsiao Chien Chen 2017-11-30

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https://ww2.mathworks.cn/matlabcentral/answers/370150-change-standard-in-hdl-workflow-adviser

Hi,

I am working on HW/SW co-design this example with ZedBoard and FMCOMMS2/3/4, but I would like to have a control signal coming out from the Pmod port. (Whether JA/JB/JC/JD is fine.) I succeed in assign the signal to the Pmod port but the voltage is too low to drive my next stage mux, i.e. I need 3.3V from the Pmod but I can only get 2.5V from JA/JB port and 0.7V from JC/JD port.

I have asked the engineers from AVNET and they said the output voltage should reach 3.3V from Pmod. Besides, I have opened the bit file with my Vivado and I found that the iostandard at Pmod port is "lvcmos25", yet I could not change it into "lvcmos33".

In short, how could I do to level up my voltage coming out from Pmod with HDL workflow adviser?

Thank you very much for your help in advanced.

B.R.

Angie