Problem with 'Fine Frequency Compensation' in HW/SW QPSK transceiver using FMCOMMS1

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hoang viet 2018-2-6

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https://ww2.mathworks.cn/matlabcentral/answers/380972-problem-with-fine-frequency-compensation-in-hw-sw-qpsk-transceiver-using-fmcomms1

编辑： Noam Levine 2018-4-12

Hello,

I'm working for a project to streaming video base on Zynq and Fmscomms1 hardware, we base on the hardware-software co-design example

https://www.mathworks.com/help/supportpkg/xilinxzynqbasedradio/examples/hw-sw-co-design-qpsk-transmit-and-receive-using-analog-devices-ad9361-ad9364.html?searchHighlight=hw%252Fsw%2520qpsk&s_tid=doc_srchtitle .

I generates the hdl DSP ipcore from matlab block and now able to transmit and receive data through it. But when I try to aging the stable of system by start transmit and receive data loopback a hundred of time and then disable/reset channel and re-enable again. I meet a problem the receiver cannot see data forever after several time up/down the channel.

So I try to dig in into the DSP hdl code generated by HDL coder, this is how i debug it. I capture the data in each IP core block when system is failed and using simulink to analyze the correct of data. And I found the data from output port of Fine Frequency Compensation is wrong when system failed(receiver cannot see data) while data from coarse frequency block still right (able to decode by matlab).

I'm wondering the Fine Frequency Block generated by HDL coder is wrong, so do you have any ideas for me to continuous debug this system ?

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Noam Levine 2018-4-12

编辑：Noam Levine 2018-4-12

Can you verify which version of MATLAB you are using? Can you also please clarify which transceiver board you're using - your say you're using FMComms1, which does not have an AD9361 transceiver on it, so the example you're using won't work properly. Are you sure you're not using an FMComms2, 3, or 4?

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