Hi ChangKi,
If the model contains a loop without any real source which can start the propagation of the bus,then it becomes the expected behavior.
Even if we specify the bus data type on the ports of the subsystem, this cannot be used for bus propagation. Specifying bus data type on ports of subsystem is used only later in the propagation process for verification only.
To propagate a bus signal we either require a proper source such as a Root-level Inport, a Bus Creator, or a Constant block. If there is a loop and no real source, we can use a signal specification block.
