Hi Harry,
I am going to assume that you are using the FPGA targeting workflow only, that is you do not have access to Embedded Coder to use the HW/SW co-design workflow? The reason this is important is that in the FPGA-only workflow, currently you are unable to access more ports than the streaming I/Q data and valid ports. If you have extra information you need to bring back to the host, you will need to multiplex it with the I/Q data. You can see how we have done this with the FPGA packing subsystems. For example, perhaps you could pack the power values onto the I/Q samples when "start" is low and there is not decoded data coming back? Note though that the power values corresponding to a valid packet may need to be stored up and sent back once you have sent back the decoded data!
In the HW/SW co-design workflow, you can add as many ports as you like and assign them as AXI-lite registers, which lets you read and write memory mapped registers. You can obviously also still multiplex your information onto the I/Q data ports. To read/write the AXI-lite registers, you need to have Embedded Coder to enable External Mode operation. Once you have that up and running, you can read and write to your registers from Simulink.
Let me know if I can clarify that any more.
Cheers,
Neil
