Estimating the latency of a custom IP block in HDL Coder

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Mike Bardill
Mike Bardill 2019-1-16
评论： Bharath Venkataraman 2019-1-22
I have a Simulink design that I want to build into a custom IP block to deploy on a Zynq FPGA target using HDL Coder. The concept is that the block takes some data from Block RAM, performs some compuations on that data and saves the results in Block RAM. The design consists mainly of fixed-point embedded Matlab blocks in a Simulink subsystem. There is also a Stateflow controller that manages how the computation block takes data from Block RAM and how the results are stored back in Block RAM. The design is simulated in Simulink and functionally appears to do what is needed.
The problem is working out how the Stateflow controller knows at what point the data produced by the computation block is valid. Typically from being presented with the first item of data from Block RAM it might be many clock cycles before a valid result is produced. The Stateflow controller must store the results in Block RAM only when they are valid. The timing properties cannot be characterised by HDL Coder as there is no data available for the embedded Matlab blocks.
Is there a way to work out the latency through the model without having the characterisation data?
Alternatively is there some construct that can be built into the model that would for example produce a trigger when the first valid result becomes available?
This is very akin to using the 'FFT HDL Optimized' block in the DSP System Toolbox HDL Support library. This block displays the latency in its mask according to the particular configuration as well as providing output signals to show when valid data is available. This is exactly what I want to do in my custom IP block but I cannot see how to go about this.

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回答（1 个）

Bharath Venkataraman
One of the ways to do this is by having the computatiobn block emit a valid output signal. based on this signal, the controller can take the appropriate signal.
  2 个评论
Mike Bardill
Mike Bardill 2019-1-22
That was the idea but how does one create the valid signal? The IP might take many cycles before it produces a valid piece of data. Up to that point it willl be producing data - just not valid data. If the latency through the block is not known and cannot easily be determined then how is logic inserted that sets the valid flag true at the correct time?
Are there any examples that illustrate how to do this?
The answer could be very simple and it's just me that is not seeing it or understanding it!
Bharath Venkataraman
Bharath Venkataraman 2019-1-22
I assume that you have an idea of what the IP does and can modify it.
The easiest way is to know the latency and have the valid input signal delayed by the same latency to provide the output valid signal.
Another way is to pipeline the valid signal in parallel to the IP computation, so that the valid signal indicates valid data all the way through the IP.
In the example for the high-throughput Channelizer, the Filter bank subsystem under the PolyPhaseFilterBank subsystem shows how to pipeline the valid input along with the computation.

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