Hi,
You can open Xilinx ISE project from the link generated in HDL Workflow Advisor step 4.1, and change following two settings in the ISE project. Then ISE will not attempt to bind the I/Os to IOBs.
- Clear “add I/O buffer” (–iobuf) in synthesis settings
- Clear “trim unconnected signals” (–u) in mapping settings
Alternatively, you can create a Tcl file with following two lines to set the same settings, and attach the Tcl file in the "Additional source files" box in HDL Workflow Advisor step 4.1.
project set "Trim Unconnected Signals" "false" -process "Map"
project set "Add I/O Buffers" "false" -process "Synthesize - XST"
You can take look at this link :
Hope this helps !
