HDL Parser error: Unsupported data-type sfixed in "Fpga-in-the-loop"

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Raphael
Raphael 2013-3-19
I have some .vhd files which were not generated using HDL coder but have been successfully co-simulated using modelsim. However when I try to simulate using the FPGA-in-the-loop wizard, it seems to have problems in using the sfixed or ufixed types of variables, which use the ieee fixed_pkg library. Is there a solution for that? Did anyone manage to run .vhd files with sfixed data-type using this libraries for FIL simulations???

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回答（2 个）

Tim McBrayer
Tim McBrayer 2013-3-19
How are you getting VHDL-2008 code into Simulink in FIL mode? HDL Coder doesn't generate any 2008-specific constructs. If you are bringing it in with a Black Box, you will need to tweak how your VHDL compiler and simulator are invoked, to make sure that they are invoked in a way that enables VHDL-2008 features.
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Raphael
Raphael 2013-3-22
I'm not using the HDL coder to generate my code, I wrote it myself. Thanks for the answer anyway, I manage to solve my problem.

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Tao Jia
Tao Jia 2013-3-20
To use FPGA-in-the-Loop, the I/O port on the top-level entity must be std_logic_vector or std_logic type. The ufixed and sfixed data types you have are not supported.
To fix the problem, you can probably use To_slv function to convert those data types to std_logic_vector.
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Raphael
Raphael 2013-3-22
Thanks Tao Jia that was one of the issues, the other thing is that I needed to add the lib files along with my VHD files. I'm still trying to understand the main clock, can I configure its frequency? What is the default clock when I use the FIL Wizard?

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