Perform mapping of 16 point ifft using cosimulation
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Hi
I have successfully managed to satisfy all check points of "HDL workflow advisor" Now at mapping I am given Error as provided in snapshot that the resources are insufficient. The FPGA in use is spartan-3e with 500k gates and I think its sufficient for this task. Can any one help me in this matter?
Snapshot:
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Rob Graessle
2011-5-8
1 个投票
"IOB" refers to the input/output pins on the FPGA. So the design you are implementing has too many inputs and outputs (or the widths of the I/O signals are too large) for your particular FPGA.
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