Multibit CT DS ADC with DWA and ISI-Mitigation

This is a demonstration of digital-domain ISI-error correction for a multibit CT DS ADC. Here, the ISI-error model is discrete-time, based on [1].
The idea was inspired by [2], where the static and dynamic feedback-DAC noise was corrected by digital error correction. In [2], thermometer encoder was used in DAC and the number of correction coefficients is 3M, where M is the number of DAC unit-elements.

This demonstration shows that using dynamic element matching DAC encoder (DWA) can reduce the number of lookup-table correction coefficient from 3M to 1, which should make the ISI-error mitigation by digital error correction more viable.

The correction and calibration method demonstrated here is further documented in [3].

You need Delta-Sigma toolbox to run this demonstration.

References:
[1] L. Risbo, R. Hezar, B. Kelleci, H. Kiper, and M. Fares, “Digital approaches to ISI-mitigation in high-resolution oversampled multi-level D/A converters,” IEEE J. Solid-State Circuits, vol. 46, no. 12. Dec. 2011.
[2] M. Runge and F. Gerfers “A Digital Compensation Method Canceling Static and Non-Linear Time-Variant Feedback DAC Errors in Sigma-Delta Analog-to-Digital Converters,” in proc IEEE International Symposium on Circuits and Systems (ISCAS) 2017, May 2017.
[3] Marko Neitola, "Two-Stage Internal DAC Mismatch Mitigation for Continuous-Time Delta-Sigma Converter, " Submitted on Aug 7th 2019 to IEEE Nordic Circuits and Systems Conference 2019.