AMD Vitis Model Composer

AMD Vitis™ Model Composer is a block diagram environment used to design embedded systems with multidomain models, simulate before moving to hardware, and deploy without writing code.  Developers can design and simulate a high-performance DSP system using MATLAB, Simulink, and an AMD library of bit- and cycle-accurate models. The tool automatically generates synthesizable Hardware Description Language (HDL) code mapped to AMD pre-optimized algorithms. This HDL design can be synthesized for implementation on hardware including AMD Versal, RFSoC, and Zynq-7000 platforms.  As a result, designers can define an abstract representation of a system-level architecture and transform this single source code into a gate-level representation. Additionally, it generates an HDL testbench and enables design verification.

Vitis Model Composer includes all the functionality of Xilinx System Generator for DSP which is no longer provided as a standalone tool.

Additional Resources:

• More about Prototyping with Simulink and AMD Adaptive FPGAs and SoCs
• On-Demand Training
• Vitis Model Composer Tutorials (on GitHub)
• Main Vitis Model Composer GitHub page

Read the following user stories:

• How Liquid Instruments uses MathWorks and AMD products  User story.
• How BAE Systems uses MathWorks and AMD products User story.