Getting Started with the Avnet ZUBoard
This four-part video series takes you through a complete process of exploring, prototyping, and deploying a finite impulse response (FIR) filter onto an Avnet® ZUBoard using AMD-Xilinx® Vitis™ Model Composer. In this project, a FIR filter processes input data and the frequency response is shown on a spectrum analyzer.
Learn where to find the hardware and software products needed for a project. Download MATLAB and Simulink from MathWorks, plus Vitis Model Composer and Vivado Design Suite from AMD-Xilinx. Lastly, order the ZUBoard development kit from Avnet.
Design and Simulate an Algorithm Using Vitis Model Composer
Become familiar with the project workflow and simulate a FIR filter. Change system conditions and view simulation results. When simulation is complete, create a final IP block.
Elaborate the Design Using Vivado
Import a FIR filter IP block into AMD-Xilinx Vivado Design Suite and perform design validation. Then create a standalone design, validate it, and run behavioral simulation.
Program the Design onto an FPGA Using Vivado
Synthesize, implement, and program a FIR filter onto the Avnet ZUBoard hardware using Vivado.
