Easier HDL design and verification workflow – the Model-Based-design flavor
Overview
Join MathWorks for an insightful seminar that will transform your approach to project design. Learn how Model-Based Design (MBD) can significantly boost your productivity by enabling the generation of standard-compliant, synthesizable VHDL, Verilog, or System Verilog directly from MATLAB and Simulink. Discover how this approach helps you detect bugs earlier, allowing you to bring your projects to market with greater confidence in their quality.
Experience a live demo targeting an SoC board and explore applications across various domains such as Motor Control, Wireless Communications, Vision, and Deep Learning.
Highlights
- Automatic HDL code generation and verification out of Simulink Models
- Applying the workflow to different domains, such as Motor Control, Wireless, Vision, and Deep learning
- Motor Control demo on a commercially available SoC board
Who Should Attend
If you are:
- ASIC/FPGA Design engineer, or
- ASIC/FPGA Verification engineer, or
- Algorithm designer, or
- System Architect
this seminar will be highly beneficial for you.
About the Presenter
Baruch Mitsengendler
Baruch works with MathWorks, Germany since October 2016 as a senior application engineer. His main functions include responsibility for the different HDL related toolboxes.
Prior to joining MathWorks, Baruch was working as an ASIC design and verification engineer, both in Israel and Germany. His main working focus was wireline communication systems as well as memory products.
Baruch has a B.Sc. degree in Electrical Engineering from the Technion, Israel Institute of Technology.
