Design, analyze, and simulate analog and mixed-signal systems
Mixed-Signal Analyzer App
Use the Mixed-Signal Analyzer app to interactively visualize, analyze, and identify trends in mixed-signal data in the time and frequency domains.
The Cadence Virtuoso ADE MATLAB Integration option lets you import databases of circuit-level transient, AC, and DC, simulation results into MATLAB.
Design and simulate phase-locked loops (PLLs) at the system level. Typical architectures include integer-N PLLs with single or dual modulus prescalers, and fractional-N PLLs with accumulators or delta-sigma modulators. Verify and visualize the open-loop and closed-loop response of your designs.
ADC and DAC Design
Design and simulate analog-to-digital (ADC) and digital-to-analog (DAC) data converters at the system level. Typical architectures include flash and successive approximation register (SAR) ADCs as well as binary weighted and segmented DACs.
Building Blocks Library
Design your mixed-signal system using building blocks such as charge pumps, loop filters, phase frequency detectors (PFDs), voltage-controlled oscillators (VCOs), clock dividers, and sampling clock sources, among others. You can further refine analog models at a lower abstraction level with Simscape Electrical™.
Import SPICE netlists
You can import a SPICE netlist and create or modify a linear, time-invariant circuit with parasitic elements extracted from the IC design using the Linear Circuit Wizard block.
Phase Noise and Jitter
Model aperture jitter in ADCs and specify arbitrary phase noise profiles in the frequency domain for VCOs and PLLs. Visualize the effects with the Eye Diagram block.
Measure the lock time, phase noise profile, and operating frequency of PLLs, and characterize the performance of building blocks such as VCOs, PFDs, and charge pumps. Measure AC and DC characteristics and aperture jitter of ADCs.
Integration with IC Simulation Environments
Reuse system-level mixed-signal models in your IC design environment via cosimulation or by generating a SystemVerilog module using HDL Verifier™. For the digital part of your system you can generate synthesizable HDL code using HDL Coder™.