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Data Converters

Simulate successive-approximation-register (SAR) and flash analog to digital data converters (ADC)

Simulate and analyze performance metrics of analog to digital data converters. Start from complete system-level models of typical ADC architectures, such as SAR or flash ADC. Modify ADC parameters until you reach your desired system specifications. Use Measurements and Testbenches to validate your design.


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Sampling Clock SourceGenerate clock signal with aperture jitter
Delta Sigma ModulatorModel a discrete delta sigma modulator based ADC
Flash ADCN-bit ADC with flash architecture
SAR ADCN-bit successive approximation register (SAR) based ADC
Binary Weighted DACN-bit DAC based on R-2R weighted resistor architecture
Segmented DACConvert large digital input to analog signal using arrangement of smaller DACs