Data Converters
R2026bSimulate and analyze performance metrics of analog-to-digital (ADC) and digital-to-analog (DAC) data converters. Start from complete system-level models of typical ADC or DAC architectures. Modify ADC or DAC parameters to achieve your desired system specifications.
After designing the data converter, you can validate your design using Measurements and Testbenches. You can also analyze your models using MATLAB® functions. For more information, see Analysis and Optimization.
Functions
Blocks
 | Delta Sigma Modulator | ADC based on delta-sigma modulator |
 | Continuous Time Delta Sigma Modulator | ADC based on continuous-time delta-sigma modulator (Since R2024b) |
 | DSM DAC | Model real DAC with non-idealities (Since R2026b) |
 | DT Integrator | Real discrete-time integrator for delta-sigma modulator (Since R2026a) |
 | CT Integrator | Real continuous-time integrator for delta-sigma modulator (Since R2026b) |
 | Quantizer | Multi-bit or multi-level based unified mid-tread quantization (Since R2026a) |
 | Sampling Clock Source | Generate clock signal with aperture jitter |
 | Clock Generator | Generate clock signal with one or more phases (Since R2022a) |
 | Signal Sampler | Sample incoming signal at the edge of incoming clock (Since R2022a) |
 | Flash ADC | N-bit ADC with flash architecture |
 | SAR ADC | N-bit successive approximation register (SAR) based ADC |
 | Interleaved ADC | Time-interleaved ADC model (Since R2023b) |
 | Binary Weighted DAC | N-bit DAC based on R-2R weighted resistor architecture |
 | Segmented DAC | Convert large digital input to analog signal using arrangement of smaller DACs |
Topics
- Compare SAR ADC to Ideal ADC
This example compares the SAR ADC block from Mixed-Signal Blockset™ to the ideal ADC model with impairments presented in Analyzing Simple ADC with Impairments.
- Design and Evaluate Interleaved ADC Using System Object
This example shows how to use System objects to model and evaluate the performance of an interleaved ADC.
- Effect of Metastability Impairment in Flash ADC
This example shows how to customize a flash Analog to Digital Converter (ADC) by adding the metastability probability as an impairment.
- Compare Binary-Weighted DAC to Ideal DAC
This example compares the Binary Weighted DAC block from the Mixed-Signal Blockset™ to an ideal DAC model.
- ADC Tutorial
This tutorial example shows you how to design a second-order delta-sigma analog-to-digital converter in Simulink®.
- STEP 1: System-Level Model of DSM ADC
- STEP 2: SystemVerilog Module Generation
- STEP 3: Final System-Level Model
Featured Examples
Design and Implement Delta-Sigma Modulator using Switched-Capacitor Integrator
Use the Delta Sigma Modulator Block to include a physically realizable switched-capacitor (SC) based discrete-time integrator from Mixed-Signal Blockset™. The objective is to bridge the gap between behavioral modeling and circuit-level implementation. By utilizing the Mixed-Signal Blockset™, this example demonstrates that a practical DSM ADC can be accurately modeled to achieve SNR and ENOB metrics comparable to commercial hardware, such as the TI® ADS1209 [1] which is used as a reference for this example.
Model MASH and SMASH Delta-Sigma Modulators
Model multi-stage noise-shaping (MASH) or cascade Delta-Sigma Modulators (DSM) using the Delta-Sigma Modulator block. MASH structures work by feeding the quantization error from the present stage to the next stage and combining the outputs from multiple stages in a digital cancellation logic. The advantage of cascade DSMs is that you can get the performance of higher order DSM without their stability issues.
Model Continuous-Time Band-Pass Delta-Sigma Modulator
Different ways of implementing a continuous-time (CT) band-pass delta-sigma modulator (BP-DSM) based on multi-path feedback loop or using a Finite Impulse Response (FIR) filter in the feedback path.
Model Continuous-Time Low-Pass Delta-Sigma Modulator with Different Levels of Abstraction
Synthesize, model and simulate a third-order continuous-time (CT) low-pass delta-sigma Modulator (LP-DSM), by using various levels of abstraction, starting from ideal/system-level model using Mixed-Signal Blockset's DSM block to a schematic model based on Simscape blocks.
Analyzing Simple ADC with Impairments
Implement a basic ADC using a Zero-Order Hold block as a sampler. This simple ADC highlights some of the typical impairments introduced in an analog-to-digital converters such as aperture jitter, nonlinearity, quantization, and saturation. This example shows how to measure the effects of such impairments using a Spectrum Analyzer block and the ADC AC Measurement block from the Mixed-Signal Blockset™. To better approximate real-world performance, you can individually enable the impairments in the model.
Design and Evaluate Successive Approximation ADC Using Stateflow
Design and evaluate a 12-bit successive approximation register ADC.
Subranging ADC
Model a 6-bit Subranging ADC with pipelining and an error correcting second stage.
Design and Evaluate Interleaved ADC
This interleaved ADC model highlights some of the typical impairments introduced by data converters and their effects on a larger system.
Oversampling Interpolating DAC
Model a 12-bit Oversampling Interpolating DAC.
Design and Evaluate Segmented DAC
Design and evaluate a segmented DAC using reference architecture and validate the DAC using the DAC Testbench. For this example, use the datasheet of AD9775. This is a commercial, off-the-shelf 14-bit DAC from Analog Devices.
Design a 5th-Order Continuous-Time Delta-Sigma Modulator
Walks you through the complete design of a wideband continuous-time delta-sigma modulator (CT-DSM) targeting the Analog Devices AD9262 specifications. You will start from system-level requirements, synthesize a noise transfer function, derive continuous-time coefficients, build a Simulink model, and validate performance against the datasheet.
Verify Multi-Path ADC in Architectural, Behavioral, and Circuit Domains
Use a time-interleaved analog to digital converter (ADC) from Mixed-Signal Blockset™ to develop an offset and gain calibration engine for mismatched interleaved ADC paths. For an architectural representation of time-interleaved ADC for IBIS-AMI export, see the ADC IBIS-AMI Model based on COM and Architectural 112G PAM4 ADC-Based SerDes Model examples.
