Innovative GSPS Signal Processing Solution with MATLAB Simulink for FPGA SoC

Overview

Join us for a detailed webinar that addresses the challenges and solutions associated with processing incoming high-speed data for pivotal applications such as 5G New Radio(NR), radar, and signal intelligence.The advancements in analog-to-digital converters (ADCs) have been instrumental in the development of new DSP algorithms that can sustain the demanding performance requirements of these sophisticated applications.Our discussion will focus on effective strategies for modeling, exploring, and simulating hardware architecture options, as well as methods for generating synthesizable VHDL and Verilog code.

Highlights

In this webinar, you will learn how to:

• Apply Model-Based Design methodology to model and simulate DSP algorithms for effectively targeting FPGA/ASIC platforms.
• Utilize a Digital Down Conversion (DDC) example to examine and enable efficient sample- and frame-based processing.
• Analyze and enhance hardware design with a focus on latency, throughput, and resource usage.
• Generate readable, synthesizable VHDL and Verilog code for FPGA deployment.

About the Presenter 

Nadereh Rooein, Principal Application Engineer at MathWorks 

Nadereh has extensive experience in ASIC/FPGA design and verification.She previously worked for Ericsson on 3G technology and Teradyne for automatic test equipment of large ASICs.At MathWorks, she has over 18 years of experience helping customers across various industries adopt our HDL workflow for designing, implementing, and verifying ASICs/FPGAs/SoCs.She holds a Master of Electronic Engineering from Chalmers University of Technology, Gothenburg, Sweden.